The present invention relates to flash memory.
Flash memories are commonly applicable to mass storage subsystems for electronic devices employed in mobile communications, game sets, and so forth. Such subsystems are usually implemented as either removable memory cards that can be inserted into multiple host systems or as non-movable embedded storage within the host systems. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash memories are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Therefore, flash memories do not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. The typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks. Each block is further partitioned into one or more addressable sectors or pages that are the basic unit for read and program functions.
Flash memories basically have their own functional operations of reading, writing (or programming), and erasing. Another function is to maintain the integrity of data stored in the flash memory. To this end, the subsystem typically includes an error detection and correction unit. However, at times even use of the error detection and correction is not sufficient. Namely, as a cell is erased, programmed, etc. the cell degrades, and a cell may degrade to the point of being unusable for storing data. Accordingly, flash memories by perform a copy back operation to move data from one erasable block including one or more unusable cells to a free data block that does not include an unusable cell. To manage these bad blocks, a spare area of the memory array may include bad block flags corresponding to each block. The bad block flag indicates whether the corresponding erasable block is bad (i.e., includes an unusable cell) or not.
FIG. 1 illustrates a conventional flash memory system. As shown, a controller 120 controls the operation of one or more flash memory devices 125 via an input/output (I/O) interface 118. In FIG. 1, only one flash memory device 125 has been shown for the sake of clarity. The flash memory device includes an array 100 of transistor cells, each cell capable of non-volatile storage of one or more bits of data. The arrays of cells are partitioned into groups of cells referred to as erasable blocks 116. Each block 116 is further partitioned (not shown) into one or more addressable sectors or pages that are the basic unit for read and program functions. As further shown, the array 100 is divided into a main area 110 and a spare area 112. The main area 310 stores data as is well-known, and the spare area 112 includes bad block flags 114 corresponding to each block 116. The bad block flag 114 indicates whether the corresponding erasable block 116 is bad (i.e., includes an unusable cell) or not.
An address decoding and control unit receives controls signals over the input/output interface 118 (e.g., a bus and/or buffer) from the controller 120. These signals may include, for example, a chip select signal (CS) used to active the flash memory, a read strobe (RS) signal used to indicate a data read operation, a write strobe (WS) signal used to indicate a write operation, and an address signal used to indicate the address of the memory array 100 associated with the read or write operation. Based on the control signals, the address decoding and control unit 108 generates control signals for controlling the memory array 100, a page buffer unit 102 and a column gating unit 104 in the well-known manner. For example, the address and decoding control unit 108 controls the memory array 100, page buffer unit 102 and column gating unit 104 to perform read, program and erase operations consistent with read and write operations indicated by the control signals.
The page buffer unit 102 includes a plurality of page buffers (not shown), each associated with a column or columns of the memory array 100. Each page buffer stores data read from or for being written to a memory cell or cells in the associated column of the memory array 100. Each page buffer selectively operates based on the control signals from the address decoding and control unit 108. The column gating unit 104 selectively outputs the data from or inputs data to one of the page buffers in the page buffer unit 102 based on the control signals from the address decoding and control unit 108. The column selecting unit 104 is connected to the I/O interface via an error detection and correction unit 106, sends the read data over the I/O interface 118, and receives data for writing via the I/O interface 118. It will be appreciated that the data may be received and sent by the controller 120 or another external device.
The error detection and correction (ECC) unit 106 detects errors in the data to be written into or read from the memory array 110, and corrects the errors according to any well-known error correction scheme. However, because of a degraded memory cell, the errors in read data may be too large for the ECC unit 106 to correct. This ECC failure may be reported to the controller 120, which recognizes the read cells as including a cell which has degraded to being unusable—an unusable cell.
The controller 120 also detects unusable cells of the array 300 in other ways. For example, one technique for detecting such cells is to verify that program and/or erase operations have completed satisfactorily. Any well-known verify technique may be used. A verification failure results in a determination that the cell or cells in question are unusable.
If the controller 120 detects unusable cells, the bad block flag 114 in the spare area 112 associated with the block 116 including the detected unusable cells is set. The controller 120 may also conduct a copy back operation in which the data of the block marked as bad is copied to a free block, which does not include unusable cells. For example, assume the nth page of a block is determined to include unusable cells as a result of a failed verification process during a write operation to the nth page. The controller 120 issues control signals to copy the first to (n−1)th pages of the block to the first to (n−1)th pages of a free block, writes the nth page in the free block pursuant to the write operation, and copies the remaining n+1, n+2, etc. pages of the unusable block to the free block. It will be appreciated that the controller 120 may maintain, for example, a table or other management data regarding which blocks are free. This management information may be stored locally at the controller, in the flash memory device, etc. The controller 120 also sets the bad block flag for the unusable block. For example, the memory cell forming the bad block flag may be programmed to indicate that the corresponding block is unusable.
As discussed above, degradation causes the transistor cell to become unusable. In particular, over the course of many program and erase cycles, the erasure and program threshold voltages change. FIG. 2A illustrates the erasure and program threshold voltages of a useable transistor cell. As shown a large margin between the erasure and program threshold voltages initially exists, and it is easier to distinguish if the cell is erased or programmed. However, over the course of many program and erase cycles, the margin between the erasure and program threshold voltages decreases, and may decrease to a point where the margin is no longer sufficient to provide for consistently distinguishing between the erased and programmed states.
This situation becomes more pronounced with multiple level transistor cells, also referred to as MLCs. Unlike the single level cell (SLC) discussed above with respect to FIG. 2A, an MLC includes more than two threshold voltage states. A SLC includes two threshold voltage states where each state represents either a logic 1 or a logic 0 (i.e., a SLC stores 1 bit of data). A four level MLC includes four threshold states, and each state represents two bits of data. FIG. 2B illustrates the threshold states and associated bits for an example, useable four level MLC. As will be appreciated, the threshold margin between these states is significantly less than for a SLC. As a result, a MLC may become unusable in less time than an SLC as a result of degradation. Furthermore, because an MLC stores more data than an SLC, the loss of a MLC results in a greater loss of storage capacity.